DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 157
DS26524DK
Manufacturer Part Number
DS26524DK
Description
KIT DESIGN FOR DS26524
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26524G.pdf
(273 pages)
Specifications of DS26524DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
DS26524
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC
condition was detected and then removed.
Bit 6: Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match
condition was detected and then removed.
Bit 5: Loop-Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down
condition was detected and then removed
Bit 4: Loop-Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up
condition was detected and then removed.
Bit 3: Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLK pin
has not transitioned for one channel time.
Bit 2: Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as
defined in the
Bit 1: Loop-Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loop-
down code as defined in the
Bit 0: Loop-Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop-up code
as defined in the
LORCC
T1RSCD1:T1RSCD2
7
0
T1RUPCD1:T1RUPCD2
RLS3 (T1 Mode)
Receive Latched Status Register 3
092h + (200h x n): where n = 0 to 3, for Ports 1 to 4
LSPC
T1RDNCD1:T1RDNCD2
6
0
registers is being received.
LDNC
5
0
register is being received.
157 of 273
LUPC
register is being received.
0
4
RLS3
for E1 mode.
LORCD
3
0
LSPD
2
0
LDND
1
0
LUPD
0
0
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