DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 259
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DS26524DK
Manufacturer Part Number
DS26524DK
Description
KIT DESIGN FOR DS26524
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26524G.pdf
(273 pages)
Specifications of DS26524DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
DS26524
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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12.2
Table 12-4. JTAG Interface Timing
(V
Note 1:
Figure 12-12. JTAG Interface Timing Diagram
JTCLK Clock Period
JTCLK Clock High:Low Time
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
JTCLK to JTDO High-Impedance Delay
JTRST Width Low Time
DD
= 3.3V ±5%, T
JTDI, JTMS, JTRST
JTAG Interface Timing
Clock can be stopped high or low.
PARAMETER
JTRST
JTCLK
JTDO
A
= -40°C to +85°C for DS26524GN.) (See
t6
t7
t2
SYMBOL
t2:t3
t1
t4
t5
t6
t7
t8
259 of 273
t4
t1
(Note 1)
t5
CONDITIONS
Figure
t3
t8
12-12.)
DS26524 Quad T1/E1/J1 Transceiver
MIN
100
50
5
2
2
2
1000
TYP
500
MAX
50
50
UNITS
ns
ns
ns
ns
ns
ns
ns
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