DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 227

• Manufacturer Part Number: DS26524DK
• Description: KIT DESIGN FOR DS26524
• Manufacturer: Maxim Integrated Products

Specifications of DS26524DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: DS26524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to
be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be
cleared and set again for subsequent loads.
Bit 6:Transmit Invert Data Enable (TINV).
Bit 5:Receive Invert Data Enable (RINV).
Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive
circuits. See
Table 9-22. BERT Pattern Select
Bit 1: Load Bit and Error Counter (LC). A low-to-high transition latches the current bit and error counts into the
registers BBC1, BBC2, BBC3,
toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set
again for subsequent loads.
Bit 0: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes
to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
PS2
0
0
0
0
1
1
1
1
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
0 = do not invert the incoming data stream
1 = invert the incoming data stream
PS1
0
0
1
1
0
0
1
1
Table
TC
7
0
PS0
0
1
0
1
0
1
0
1
9-22.
Pseudorandom 2E7-1
Pseudorandom 2E11-1
Pseudorandom 2E15-1
Pseudorandom Pattern QRSS. A 2
Repetitive Pattern
Alternating Word Pattern
Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is
byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance
for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25
(November 1993).
Pseudorandom 2E-9-1
BC1
BERT Control Register 1
1105h + (10h x n): where n = 0 to 3, for Ports 1 to 4
TINV
6
0
BBC4
and BEC1, BEC2, and BEC3, and clears the internal count. This bit should be
RINV
5
0
227 of 273
PS2
0
4
PATTERN DEFINITION
20
- 1 pattern with 14 consecutive zero restriction.
PS1
3
0
PS0
2
0
LC
1
0
RESYNC
0
0