STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 145
STEVAL-IFS003V1
Manufacturer Part Number
STEVAL-IFS003V1
Description
BOARD STLM75/STDS75/ST72F651
Manufacturer
STMicroelectronics
Datasheets
1.STLM75DS2F.pdf
(40 pages)
2.STDS75M2F.pdf
(39 pages)
3.STEVAL-IFS003V1.pdf
(161 pages)
4.STEVAL-IFS003V1.pdf
(4 pages)
Specifications of STEVAL-IFS003V1
Design Resources
STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
Sensor Type
Temperature
Sensing Range
-55°C ~ 125°C
Interface
I²C
Voltage - Supply
7.5 V ~ 19 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651, STDS75, STLM75
Silicon Manufacturer
ST Micro
Silicon Core Number
STLM75/STDS75 And ST72F651AR6
Kit Application Type
Sensing - Temperature
Application Sub Type
Temperature Sensor
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6238
- STLM75DS2F PDF datasheet
- STDS75M2F PDF datasheet #2
- STEVAL-IFS003V1 PDF datasheet #3
- STEVAL-IFS003V1 PDF datasheet #4
- Current page: 145 of 161
- Download datasheet (3Mb)
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I
Subject to general operating conditions for V
f
Figure 91. Typical Application with I
Notes:
1. Data based on standard I
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
t
OSC
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
t
su(SDA)
t
t
su(STA)
su(STO)
t
t
h(SDA)
h(STA)
r(SDA)
r(SCL)
f(SDA)
SDA
SCK
f(SCL)
I
C
, and T
2
t
C BUS
f(SDA)
b
2
C - Inter IC Control Interface
t
A
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
h(STA)
unless otherwise specified.
START
4.7kΩ
t
w(SCKH)
t
r(SDA)
V
2
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7kΩ
V
DD
t
su(SDA)
2
t
r(SCK)
C Bus and Timing Diagram
100Ω
100Ω
Doc ID 7215 Rev 4
t
h(SDA)
t
DD
f(SCK)
DD
,
SDAI
SCLI
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI). The ST7 I
requirements of the Standard I
protocol described in the following table.
ST72XXX
Standard mode I
Min
250
0
4.7
4.7
4.0
4.7
4.0
4.0
DD
3)
.
1)
4)
Max
1000
300
400
2
1)
C
t
su(STA)
20+0.1C
20+0.1C
t
su(STO)
Min
100
0
Fast mode I
1.3
0.6
0.6
0.6
0.6
1.3
2
2)
C interface meets the
1)
t
w(STO:STA)
STOP
2
b
b
C communication
REPEATED START
ST72651AR6
Max
900
300
300
400
2
C
3)
1)
START
145/161
Unit
ms
pF
μs
ns
μs
ns
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