EVAL-ADUC812QS Analog Devices Inc, EVAL-ADUC812QS Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADUC812QS
• Description: KIT DEV FOR ADUC812 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QS

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC812

SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general-purpose register banks reside in the special function register (SFR) area.
The SFR registers include control, configuration, and data registers that provide an interface between the CPU and other on-chip
peripherals.
Figure 4 shows a full SFR memory map and SFR contents on reset. Unoccupied SFR locations are shown dark shaded (NOT USED).
Unoccupied locations in the SFR address space are not implemented, i.e., no register exists at this location. If an unoccupied
location is read, an unspecified value is returned. SFR locations reserved for on-chip testing are shown lighter shaded (RESERVED)
and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by
addressable SFRs are those whose address ends in 0H or 8H.
REV. E
SFR MAP KEY:
SFR NOTES
1
2
3
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
THE PRIMARY FUNCTION OF PORT 1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS
ON THESE PORT PINS, WRITE A “0” TO THE CORRESPONDING PORT 1 SFR BIT.
PRE2
ADCI
MDO
SM0
ISPI
TF2
PSI
TF1
RD
CY
EA
0
0
0 F6H
0
0 E6H
0
0
0
0
0
1
1
0
1 96H
0
1 86H
FEH
EEH
DEH
D6H
CEH
C6H
BEH
B6H
AEH
A6H
9EH
8EH
WCOL
PADC
EADC
PRE1
EXF2
MDE
DMA
SM1
TR1
WR
AC
0
0 F5H
0
0 E5H
0
0
0
0
0
1
0
0
1 95H
0
1 85H
1
CCONV
FDH
EDH
DDH
D5H
CDH
C5H
BDH
B5H
ADH
A5H
9DH
8DH
RCLK
PRE0
MCO
SPE
SM2
PT2
ET2
TF0
F0
T1
0
0
0 F4H
0 ECH
0 E4H
0
0
0
0 C4H
0
1
1 A4H
0
1 94H
0
1 84H
SCONV
FCH
DCH
D4H
CCH
BCH
B4H
ACH
9CH
8CH
TCLK
SPIM
RS1
REN
MDI
TR0
PS
ES
T0
0
0 F3H
0
0 E3H
0
0
0
0
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
EBH
DBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
EXEN2
WDR1
CPOL
I2CM
INT1
CS3
RS0
PT1
ET1
TB8
IE1
Figure 4. Special Function Register Locations and Reset Values
SFR ADDRESS
DEFAULT VALUE
0
0 F2H
0 EAH
0 E2H
0
0
0
0
0
1
0
1 A2H
0
1 92H
0
1 82H
MNEMONIC
FAH
DAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS
WDR2
INT0
RB8
CS2
TR2
PX1
EX1
OV
IT1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
A1H
99H
91H
89H
81H
I2CTX
SPR1
CNT2
T2EX
WDS
CS1
PT0
TxD
ET0
IE0
FI
TI
THESE BITS ARE CONTAINED IN THIS BYTE.
0
0 F0H
0 E8H
0 E0H
0
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
98H
90H
88H
SPR0
CAP2
WDE
CS0
RxD
PX0
EX0
I2CI
IT0
T2
89H
RI
P
IE0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
88H
IT0
0
ADCCON2
B0H
A8H
F8H
F0H
E8H
E0H
D8H
D0H
C8H
C0H
B8H
A0H FFH
98H
90H
88H
80H
SPICON
I2CCON
WDCON
T2CON
SCON
TCON
PSW
ACC
P1
–11–
P3
P2
P0
IP
IE
B
1, 3
88H
1
1
1
1
1
1
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
00H
FFH
FFH
00H
TCON
1
1
1
1
1
1
1
1
1
00H
ADCDAT AL
ADCOFSL
F9H
F1H
RESERVED
RESERVED
D9H
RESERVED
B9H
A9H
99H
89H
81H
RESERVED
NOT USED
NOT USED
NOT USED
NOT USED
DAC0L
ECON
TMOD
SBUF
IE2
SP
00H
00H
00H
00H
00H
00H
00H
07H
2
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
ADCOFSH
ADCDAT AH
FAH
9AH
F2H
RESERVED
RESERVED
DAH 00H
D2H
CAH 00H
BAH 52H
8AH
82H
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
RCAP2L
DAC0H
I2CDAT
ETIM1
DMAL
DPL
TL0
00H
00H
20H
00H
00H
00H
2
ADCGAINL
FBH
F3H
RESERVED
RESERVED
RESERVED
D3H
CBH 00H
BBH 04H
9BH
8BH
83H
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
RCAP2H
I2CADD
DAC1L
ETIM2
DMAH
DPH
TL1
00H
00H
00H
55H
00H
00H
2
ADCGAINH
FCH
F4H
D4H
CCH 00H
C4H C9H
BCH 00H
8CH
84H
RESERVED
RESERVED
RESERVED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
EDATA1
DAC1H
DMAP
ETIM3
DPP
TL2
TH0
00H
00H
00H
00H
00H
2
ADCCON3
DACCON
FDH 04H
F5H
RESERVED
RESERVED
RESERVED
CDH 00H
RESERVED
BDH 00H
8DH
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
RESERVED
RESERVED
EDATA2
TH2
TH1
00H
00H
BEH 00H
ADuC812
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
C6H
“1”
RESERVED
RESERVED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
RESERVED
EDATA3
EDARL
i.e., the bit
00H
ADCCON1
F7H
EFH
RESERVED
DFH DEH
RESERVED
RESERVED
RESERVED
BFH
87H
PSMCON
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
EDATA4
SPIDAT
PCON
00H
20H
00H
00H