EVAL-ADUC812QS Analog Devices Inc, EVAL-ADUC812QS Datasheet - Page 31

• Manufacturer Part Number: EVAL-ADUC812QS
• Description: KIT DEV FOR ADUC812 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QS

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC812

Bit
7
6
5
4
3
2
1
0
Timer/Counters 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined to be a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
REV. E
TCON
SFR Address
Power-On Default Value
Bit Addressable
*These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
T
F
1
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
T
R
1
Timer/Counter 0 and
1 Control Register
88H
00H
Yes
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1,
depending on bit IT1 state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0,
depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt
was transition activated. If level activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
T
F
0
Table XVI. TCON SFR Bit Designations
T
R
0
–31–
I
E
1
*
I
T
1
*
I
E
0
*
ADuC812
I
T
0
*