EVAL-ADUC812QS Analog Devices Inc, EVAL-ADUC812QS Datasheet - Page 42

• Manufacturer Part Number: EVAL-ADUC812QS
• Description: KIT DEV FOR ADUC812 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QS

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC812

ADuC812
As an alternative to providing two separate power supplies, the
user can help keep AV
and/or ferrite bead between it and DV
AV
shown in Figure 44. With this configuration, other analog
circuitry (such as op amps, voltage reference, and so on) can be
powered from the AV
want to include back-to-back Schottky diodes between AV
and DV
transient conditions that could separate the two supply voltages
momentarily.
Notice that in both Figure 43 and Figure 44, a large value (10 µF)
reservoir capacitor sits on DV
sits on AV
located at each V
tice, be sure to include all of these capacitors, and ensure the
smaller capacitors are close to each AV
short as possible. Connect the ground terminal of each of these
capacitors directly to the underlying ground plane. Finally, it
should also be noted that, at all times, the analog and digital
ground pins on the ADuC812 must be referenced to the same
system ground reference point.
Power Consumption
The currents consumed by the various sections of the ADuC812
are shown in Table XXVII. The CORE values given represent
the current drawn by DV
age Reference) are pulled by the AV
in software when not in use. The other on-chip peripherals
(watchdog timer, power supply monitor, and so on) consume
negligible current and are therefore lumped in with the CORE
operating current here. Of course, the user must add any
currents sourced by the DAC or the parallel and serial I/O pins,
in order to determine the total current needed at the ADuC812’s
supply pins. Also, current drawn from the DV
increase by approximately 10 mA during Flash/EE erase and
program cycles.
DD
separately to ground. An example of this configuration is
Figure 44. External Single-Supply Connections
DD
DD
in order to protect from power-up and power-down
0.1 F
+
–
DIGITAL SUPPLY
. Also, local small value (0.1 µF) capacitors are
DD
pin of the chip. As per standard design prac-
DD
10 F
DD
supply line as well. The user will still
DD
quiet by placing a small series resistor
48
20
34
21
35
47
, while the rest (ADC, DAC, Volt-
DV
DGND
DD
BEAD
DD
ADuC812
and a separate 10 µF capacitor
DD
DD
DD
1.6
AGND
AV
pin and can be disabled
, and then decoupling
pin with trace lengths as
DD
5
6
10 F
DD
0.1 F
supply will
DD
–42–
CORE
CORE
ADC
DAC (Each)
Voltage Ref
Since operating DV
speed, the expressions for CORE supply current in Table XXVII
are given as functions of MCLK, the oscillator frequency. Plug
in a value for MCLK in hertz to determine the current consumed
by the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. The internal voltage refer-
ence is automatically enabled whenever either the ADC or at
least one DAC is enabled. And again, do not forget to include
current sourced by I/O pins, serial port pins, DAC outputs, and
so forth, plus the additional current drawn during Flash/EE
erase and program cycles.
A software switch allows the chip to be switched from normal
mode into idle mode, and also into full power-down mode.
Below are brief descriptions of power-down and idle modes.
In idle mode, the oscillator continues to run but is gated off to
the core only. The on-chip peripherals continue to receive the
clock, and remain functional. Port pins and DAC output pins
retain their states in this mode. The chip will recover from idle
mode upon receiving any enabled interrupt, or upon receiving a
hardware reset.
In full power-down mode, the on-chip oscillator stops, and all
on-chip peripherals are shut down. Port pins retain their logic levels
in this mode, but the DAC output goes to a high impedance
state (three-state). The chip will only recover from power-down
mode upon receiving a hardware reset or when power is cycled.
During full power-down mode, the ADuC812 consumes a total
of approximately 5 µA.
(Normal Mode) (1.6 nAs × MCLK) + (0.8 nAs × MCLK) +
(Idle Mode)
Table XXVII. Typical I
DD
V
6 mA
(0.75 nAs × MCLK) + (0.25 nAs × MCLK) +
5 mA
1.3 mA
250 µA
200 µA
DD
current is primarily a function of clock
= 5 V
DD
of Core and Peripherals
V
3 mA
3 mA
1.0 mA
200 µA
150 µA
DD
= 3 V
REV. E