OM11027 NXP Semiconductors, OM11027 Datasheet
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LPC2939 ARM9 microcontroller with CAN, LIN, and USB Rev. 03 — 7 April 2010 1. General description The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...
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... NXP Semiconductors Other peripherals: One 10-bit ADC with 5.0 V measurement range and eight input channels with conversion times as low as 2.44 s per channel Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an additional 16 analog inputs with conversion times as low as 2.44 s per channel. ...
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... NXP Semiconductors 40 C to +85 C ambient operating temperature range 3. Ordering information Table 1. Ordering information Type number Package Name Description LPC2939FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 1.4 mm 3.1 Ordering options Table 2. Part options Type number ...
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... NXP Semiconductors 4. Block diagram LPC2939 VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT TIMER0/1 MTMR PWM0/1/2/3 3.3 V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 networking subsystem GLOBAL ACCEPTANCE FILTER UART/LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for LQFP208 package 5.2 Pin description 5.2.1 General description The LPC2939 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each, port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [1] P2[23]/SCS1[0]/ 11 GPIO 2, pin 23 PCAP3[0]/D21 [1] P3[6]/SCS0[3]/ 12 GPIO 3, pin 6 PMAT1[0]/TXDL1 [1] P3[7]/SCS2[1]/ 13 GPIO 3, pin 7 PMAT1[1]/RXDL1 [1] P0[30]/CAP0[2]/ 14 GPIO 0, pin 30 MAT0[2] [1] P0[31]/CAP0[3]/ 15 GPIO 0, pin 31 MAT0[3] [1] P2[24]/SCS1[1]/ ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) P4[8]/A22/DSR1 38 GPIO 4, pin ground for I/O SS(IO) [1] P2[27]/CAP0[3]/ 40 GPIO 2, pin 27 MAT0[3]/EI7 [1] P5[8]/D20/U0OUT2 41 GPIO 5, pin 8 [1] P1[27]/CAP1[2]/ 42 GPIO 1, pin 27 TRAP2/PMAT3[3] [1] P1[26]/PMAT2[0]/ 43 GPIO 1, pin 26 TRAP3/PMAT3[2] ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [1] P4[12]/BLS0 64 GPIO 4, pin 12 [1] P2[1]/MAT2[1]/ 65 GPIO 2, pin 1 TRAP2/D9 [1] P5[12]/D24 66 GPIO 5, pin 3.3 V power supply for I/O DD(IO) [1] P4[1]/A9 68 GPIO 4, pin 1 [1] P3[10]/SDI2/ 69 GPIO 3, pin 10 ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [1] P2[4]/MAT1[0]/ 94 GPIO 2, pin 4 EI0/D12 [1] P2[5]/MAT1[1]/ 95 GPIO 2, pin 5 EI1/D13 [1] P1[9]/SDO1/ 96 GPIO 1, pin 9 RXDL1/CS1 V 97 ground for I/O SS(IO) [1] P1[8]/SCS1[0]/ 98 GPIO 1, pin 8 TXDL1/CS0 [1] P1[7]/SCS1[3]/RXD1/ 99 GPIO 1, pin 7 ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) V 120 ground for digital core SS(CORE) V 121 1.8 V power supply for digital core DD(CORE) [1] P1[0]/EI0/ 122 GPIO 1, pin 0 PMAT3[0]/A0 [1] P2[10]/USB_INT1/ 123 GPIO 2, pin 10 PMAT0[2]/SCS0[0] [1] P2[11]/USB_RST1/ ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [1] P5[6]/D18/RI0 148 GPIO 5, pin 6 [1] P4[14]/BLS2 149 GPIO 4, pin 14 [1] P0[5]/IN0[1]/ 150 GPIO 0, pin 5 PMAT0[3]/D29 [1] P5[14]/ 151 GPIO 5, pin 14 USB_SSPND1/RTS0 V 152 3.3 V power supply for I/O ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [4] P0[13]/IN1[5]/ 175 GPIO 0, pin 13 PMAT1[3]/A11 V 176 3.3 V power supply for I/O DD(IO) [1] P4[11]/WE/CTS0 177 GPIO 4, pin 11 [4] P0[14]/IN1[6]/ 178 GPIO 0, pin 14 PMAT1[4]/A12 [1] P5[11]/D23/DCD0 ...
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... NXP Semiconductors Table 3. LQFP208 pin assignment Pin name Pin Description Function 0 (default) [4] P0[20]/IN2[4]/ 200 GPIO 0, pin 20 PMAT2[2]/A16 [4] P0[21]/IN2[5]/ 201 GPIO 0, pin 21 PMAT2[3]/A17 [4] P0[22]/IN2[6]/ 202 GPIO 0, pin 22 PMAT2[4]/A18 V 203 ground for I/O SS(IO) [4] P0[23]/IN2[7]/ 204 ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The LPC2939 consists of: • An ARM968E-S processor with real-time emulation support • An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers • Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control SubSystem (PCRSS) • ...
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... NXP Semiconductors The ARM968E-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions or to applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM968E-S processor has two instruction sets: • ...
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Memory map LPC2939 0xFFFF FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature ...
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... NXP Semiconductors 6.6 Reset, debug, test, and power description 6.6.1 Reset and power-up behavior The LPC2939 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See Section 9 the reset pin ...
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... NXP Semiconductors 6.6.3.1 ETM/ETB The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace buffer. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand. The ETB stores trace data produced by the ETM ...
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... NXP Semiconductors Two of the base clocks generated by the CGU0 are used as input into a second, dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate two base clocks for the USB controller and one base clock for an independent clock output ...
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... NXP Semiconductors 6.7.2 Base clock and branch clock relationship Table 7 contains an overview of all the base blocks in the LPC2939 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description ...
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... NXP Semiconductors Table 7. Base clock BASE_MSCSS_CLK BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK - BASE_ICLK1_CLK [1] This clock is always on (cannot be switched off for system safety reasons). [2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock source. See [3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU, and PMU have their own clock source ...
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... NXP Semiconductors 6.8 Flash memory controller The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the bootloader. Flash memory contents can be protected by disabling JTAG access ...
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... NXP Semiconductors With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer primary buffer, hit data can be copied to the secondary buffer line, which allows the flash to start a speculative read of the next flash word. Both buffer lines are invalidated after: • ...
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... NXP Semiconductors Table 10. Sector number The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector’s address space. Note that the index sector, once programmed, cannot be erased. Any flash operation must be executed out of SRAM (internal or external) ...
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... NXP Semiconductors 6.8.5 Clock description The flash memory controller is clocked by CLK_SYS_FMC, see 6.8.6 EEPROM EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller. ...
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... NXP Semiconductors Table 11. 32-bit system address bit field and Table 12. CS[2:0] 000 001 010 011 100 101 110 111 6.9.2 Pin description The external static-memory controller module in the LPC2939 has the following pins, which are combined with other functions on the port pins of the LPC2939. ...
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... NXP Semiconductors WSTOEN = 3, WST1 = 6 Fig 5. Reading from external memory A timing diagram for writing to external memory is shown In between wait state settings is indicated with arrows. WSTWEN = 3, WST2 = 7 (1) BLS has the same timing configurations that use the byte lane enable signals to connect to write enable (8 bit devices). ...
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... NXP Semiconductors Usage of the idle/turn-around time (IDCY) is demonstrated In are added between a read and a write cycle in the same external memory device. CLK(SYS WSTOEN = 2, WSTWEN = 4, WST1 = 6, WST2 = 4, IDCY = 5 Fig 7. Reading/writing external memory Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function ...
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... NXP Semiconductors 6.10.2 Clock description The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see Section 6.7.2. 6.11 USB interface The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic configuration of the devices ...
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... NXP Semiconductors • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a • Hardware support for Host Negotiation Protocol (HNP) • Includes a programmable timer required for HNP and Session Request Protocol (SRP) • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev ...
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... NXP Semiconductors Table 14. USB OTG port pins …continued Pin name Direction USB_CONNECT2 O USB_UP_LED2 O I USB_PWRD2 USB_PPWR2 O USB_OVRCR2 I 6.11.5 Clock description Access to the USB registers is clocked by the CLK_SYS_USB, derived from BASE_SYS_CLK, see the USB block, BASE_USB_CLK and BASE_USB_I2C_CLK (see 6.12 General subsystem 6 ...
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... NXP Semiconductors • Programmable input level and edge polarity • Event detection maskable • Event detection is fully asynchronous clock is required The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event ...
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... NXP Semiconductors 6.13.2 Watchdog timer The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. Key features: • ...
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... NXP Semiconductors The key features are: • 32-bit timer/counter with programmable 32-bit prescaler • four 32-bit capture channels per timer. These take a snapshot of the timer value when an external signal connected to the TIMERx CAPn input changes state. A capture event may also optionally generate an interrupt. ...
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... NXP Semiconductors 6.13.3.2 Clock description The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx ( 3), see for power management. The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR. The register interface towards the system bus is clocked by CLK_SYS_PESS ...
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... NXP Semiconductors 6.13.4.2 Clock description The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx ( 1), see CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from the same base clock BASE_CLK_UART. The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx ...
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... NXP Semiconductors The SPI module’s operating mode, frame format, and word size are programmed through the SLVn_SETTINGS registers. A single combined interrupt request SPI_INTREQ output is asserted if any of the interrupts are asserted and unmasked. Depending on the operating mode selected, the SPI SCS outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI ...
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... NXP Semiconductors • All I/O pins default to input at reset to avoid any possible bus conflicts 6.13.6.1 Functional description The general-purpose I/O provides individual control over each bidirectional port pin. There are two registers to control I/O direction and output level. The inputs are synchronized to achieve stable read levels ...
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... NXP Semiconductors • Listen-only mode (no acknowledge; no active error flags) • Reception of ‘own’ messages (self-reception request) • Full CAN mode for message reception 6.14.1.1 Global acceptance filter The global acceptance filter provides look-up of received identifiers - called acceptance filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table memory, in which software maintains one to five sections of identifiers ...
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... NXP Semiconductors Table 21. Symbol LIN0/1 TXD LIN0/1 RXD 2 6.14.3 I C-bus serial I/O controllers The LPC2939 each contain two I 2 The I C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e ...
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... NXP Semiconductors • Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger- start options • One 10-bit, 400 ksamples/s, 8-channel ADC with 5 V inputs (5 V measurement range) and various trigger-start options • Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality • ...
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... NXP Semiconductors MSCSS QEI MSCSS TIMER0 MSCSS PAUSE TIMER1 Fig 8. Modulation and sampling control subsystem (MSCSS) block diagram LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB AHB-TO-APB BRIDGE ADC0 start synch start ADC1 synch start ADC2 start PWM0 ...
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... NXP Semiconductors 6.15.2 Pin description The pins of the LPC2939 MSCSS associated with the three ADC modules are described in Section Section 6.15.5.4, pins directly connected to the MSCSS timer 1 module are described in Section 6.15.6.1, and pins connected to the quadrature encoder interface are described in Section 6 ...
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... NXP Semiconductors 6.15.4.1 Functional description The ADC block diagram, functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain ...
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... NXP Semiconductors Table 23. Symbol ADC0 IN[7:0] ADC1/2 IN[7:0] ADCn_EXTSTART VREFN VREFP V DDA(ADC5V0) V DDA(ADC3V3) [1] VREFP, VREFN, V [2] The analog inputs of ADC0 are internally multiplied by a factor of 3 3.3 V, the maximum digital result is 1024 3 [3] V DDA(ADC5V0) Remark: The following formula only applies to ADC0: Voltage variations on VREFP (i ...
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... NXP Semiconductors • Six pulse-width modulated output signals • Double edge features (rising and falling edges programmed individually) • Optional interrupt generation on match (each edge) • Different operation modes: continuous or run-once • 16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods • ...
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... NXP Semiconductors APB system bus CONTROL IRQ pwm REGISTERS IRQ capt_match Fig 10. PWM block diagram The PWM block diagram in functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective ...
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... NXP Semiconductors 6.15.5.3 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted ...
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... NXP Semiconductors 6.15.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2939. external pin. Table 25. Symbol MSCSS PAUSE 6.15.6.2 Clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx ( 1), see Section 6 ...
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... NXP Semiconductors 6.15.7.1 Pin description The QEI module in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2939. Table 26. Symbol QEI0 IDX QEI0 PHA QEI0 PHB 6.15.7.2 Clock description The QEI module is clocked by CLK_MSCSS_QEI, see this clock is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK ...
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... NXP Semiconductors EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU0 REGISTERS AHB2DTL BRIDGE RGU REGISTERS POR reset from watchdog counter RST (device pin) Fig 11. PCRSS block diagram 6.16.1 Clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes ...
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... NXP Semiconductors 6.16.2 Clock Generation Unit (CGU0) The key features are: • Generation of 11 base clocks selectable from several embedded clock sources • Crystal oscillator with power-down • Control PLL with power-down • Very low-power ring oscillator, always on to provide a safe clock • ...
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... NXP Semiconductors CLOCK GENERATION UNIT (CGU0) 400 kHz LP_OSC clkout clkout120 EXTERNAL PLL OSCILLATOR clkout240 FREQUENCY MONITOR Fig 12. Block diagram of the CGU0 (see There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer) ...
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... NXP Semiconductors Configuration of the CGU0: choice can be made from the primary and secondary clock generators according to Figure 13. Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0: one of the outputs of the PLL or to LP_OSC/crystal oscillator directly ...
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... NXP Semiconductors generator. The RDET register keeps track of which clocks are active and inactive, and the appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. ...
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... NXP Semiconductors input clock CCO Fig 14. PLL block diagram Triple output phases: clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120 phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown ...
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... NXP Semiconductors 6.16.3 Clock generation for USB (CGU1) The CGU1 block is functionally identical to the CGU0 block and generates two clocks for the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and fractional divider. The PLLs used in CGU0 and CGU1 are identical (see The clock input to the CGU1 PLL is provided by one of two base clocks generated in the CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK ...
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... NXP Semiconductors • Monitor function to trace resets back to source • Register write-protection mechanism to prevent unintentional resets 6.16.4.1 Functional description Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see this table form a sort of cascade to provide the multiple levels of impact that a reset may have ...
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... NXP Semiconductors Table 31. Symbol RST 6.16.5 Power Management Unit (PMU) This module enables software to actively control the system’s power consumption by disabling clocks not required in a particular operating mode. Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2939 ...
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... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors 6.17.1 Functional description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: • Target 0 is ARM processor FIQ (fast interrupt service) • ...
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... NXP Semiconductors 7. Limiting values Table 33. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Supply pins P total power dissipation tot V core supply voltage DD(CORE) V oscillator and PLL supply DD(OSC_PLL) voltage V 3.3 V ADC analog supply DDA(ADC3V3) voltage V 5.0 V ADC analog supply ...
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... NXP Semiconductors Table 33. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD V electrostatic discharge esd voltage [1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximum input voltage is defined by V ...
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... NXP Semiconductors 8. Static characteristics Table 34. Static characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter Supplies Core supply V core supply voltage DD(CORE) I core supply current ...
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... NXP Semiconductors Table 34. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter V LOW-level input voltage IL V hysteresis voltage hys I HIGH-level input leakage ...
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... NXP Semiconductors Table 34. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter I LOW-level output current OL I HIGH-level short-circuit OHS output current ...
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... NXP Semiconductors Table 35. ADC static characteristics DDA(ADC3V3) amb Symbol Parameter V voltage on pin VREFN VREFN V voltage on pin VREFP VREFP V analog input voltage IA Z input impedance i C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) offset error gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2939_3 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption 80 I DD(CORE) (mA Conditions: T peripherals enabled but not configured to run. Fig 18 DD(CORE) (mA Conditions: T but not configured to run. Fig 19. I LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB C; active mode entered executing code from flash; core voltage 1.8 V; all ...
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... NXP Semiconductors I DD(CORE) (mA) Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run. Fig 20. 8.2 Electrical pin characteristics 500 V OL (mV) 400 300 200 100 V Fig 21. Typical LOW-level output voltage versus LOW-level output current ...
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... NXP Semiconductors 3 (V) 3.0 2.5 2.0 V Fig 22. Typical HIGH-level output voltage versus HIGH-level output current 80 I I(pd) (μ Fig 23. Typical pull-down input current versus temperature LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 1.0 2.0 3.0 = 3.3 V. DD(IO) − ...
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... NXP Semiconductors −20 I I(pu) (μA) −40 −60 −80 −100 V Fig 24. Typical pull-up input current versus temperature LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) −40 − All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 ...
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... NXP Semiconductors 9. Dynamic characteristics 9.1 Dynamic characteristics: I/O and CLK_OUT pins, internal clock, oscillators, PLL, and CAN Table 36. Dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I/O pins t HIGH to LOW transition THL ...
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... NXP Semiconductors 520 f ref(RO) (kHz) 510 500 490 480 Fig 25. Low-power ring oscillator thermal characteristics LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 03 — 7 April 2010 LPC2939 002aae373 1 ...
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... NXP Semiconductors 9.2 USB interface Table 37. Dynamic characteristics: USB pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 9.3 Dynamic characteristics: I Table 38. Dynamic characteristic 2 3 DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter t output fall time f(o) [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level. Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. Typical ratings are not guaranteed. The values listed are at room temperature (25 ...
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... NXP Semiconductors 9.5 Dynamic characteristics: flash memory and EEPROM Table 40. amb V DDA(ADC3V3) Symbol N endu t ret t prog init t wr(pg) t fl(BIST) t a(clk) t a(A) [1] Number of program/erase cycles. Table 41. amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Flash characteristics ...
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... NXP Semiconductors 9.6 Dynamic characteristics: external static memory Table 42. External static memory interface dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter T clock cycle time CLCL t internal read access time a(R)int t internal write access time a(W)int Read cycle parameters t CS LOW to address valid ...
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... NXP Semiconductors CSLOEL OE/BLS Fig 28. External memory read access CS BLS Fig 29. External memory write access LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t t CSLWEL WELWEH t WELDV t CSLDV All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 9.7 Dynamic characteristics: ADC Table 43. ADC dynamic characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter 5.0 V ADC0 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time conv 3.3 V ADC1/2 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time ...
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... NXP Semiconductors 145 core frequency (MHz) 135 125 115 105 Fig 30. LPC2939 core operating frequency versus temperature for different core voltages 145 core frequency (MHz) 135 125 115 105 Fig 31. LPC2939 core operating frequency versus core voltage for different temperatures LPC2939_3 ...
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... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2939 USB interface on a self-powered device LPC29xx Fig 33. LPC2939 USB interface on a bus-powered device LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ ...
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... NXP Semiconductors USB_RST1 USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 34. LPC2939 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 35. LPC2939 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 USB_VBUS2 Fig 36. LPC2939 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω ...
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... NXP Semiconductors 10.3 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 37. SPI timing in master mode SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 38. SPI timing in slave mode LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SDOn MSB OUT ...
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... NXP Semiconductors 10.4 XIN_OSC input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C slave mode, a minimum of 200 mV RMS is needed ...
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... NXP Semiconductors 11. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors temperature MSL: Moisture Sensitivity Level Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors 13. Abbreviations Table 46. Abbreviation ADC AF AHB AMBA APB BIST CAN CCO CISC DMA DSP DTL EMI EOP ETB ETM FDIV FIQ GPDMA GPIO LIN LSB LUT MAC MSB MSC MSCSS MTMR OHCI OTG PCR PHY PLL POR PWM QEI Q-SPI ...
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... NXP Semiconductors Table 46. Abbreviation SFSP SPI SSP TAP TCM TTL UART USB WDT 14. References [1] UM10316 — LPC29xx user manual. [2] ARM — ARM web site. [3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference manual. [4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling ...
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... NXP Semiconductors 15. Revision history Table 47. Revision history Document ID Release date LPC2939_3 20100407 • Modifications Table • USB logo added. • Document template updated. LPC2939_2 20091207 • Modifications Table LPC2939_1 20090611 LPC2939_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2.1 General description . . . . . . . . . . . . . . . . . . . . . 5 5.2.2 LQFP208 pin assignment . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 14 6.1 Architectural overview . . . . . . . . . . . . . . . . . . 14 6.2 ARM968E-S processor . . . . . . . . . . . . . . . . . . 14 6 ...
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... NXP Semiconductors 6.16.4 Reset Generation Unit (RGU 6.16.4.1 Functional description 6.16.4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 58 6.16.5 Power Management Unit (PMU 6.16.5.1 Functional description 6.17 Vectored interrupt controller . . . . . . . . . . . . . . 61 6.17.1 Functional description 6.17.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 62 7 Limiting values Static characteristics 8.1 Power consumption . . . . . . . . . . . . . . . . . . . . 70 8.2 Electrical pin characteristics . . . . . . . . . . . . . . 71 9 Dynamic characteristics ...