OM11027 NXP Semiconductors, OM11027 Datasheet - Page 34

• Manufacturer Part Number: OM11027
• Description: BOARD EVAL LPC2939
• Manufacturer: NXP Semiconductors
• Type: MCUr

Specifications of OM11027

• Contents: Board
• For Use With/related Products: LPC2939
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4787

NXP Semiconductors
LPC2939_3
Product data sheet
6.13.3.1 Pin description
The key features are:
The timers are designed to count cycles of the clock and optionally generate interrupts or
perform other actions at specified timer values, based on four match registers. They also
include capture inputs to trap the timer value when an input signal changes state,
optionally generating an interrupt. The core function of the timers consists of a 32 bit
prescale counter triggering the 32 bit timer counter. Both counters run on clock
CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this
clock. Note that each timer has its individual clock source within the Peripheral
SubSystem. In the Modulation and Sampling SubSystem each timer also has its own
individual clock source. See
The four timers in the peripheral subsystem of the LPC2939 have the pins described
below. The two timers in the modulation and sampling subsystem have no external pins
except for the pause pin on MSCSS timer 1. See
timers and their associated pins. The timer pins are combined with other functions on the
port pins of the LPC2939, see
0 to 3).
Table 16.
Symbol
TIMERx CAP[0]
TIMERx CAP[1]
TIMERx CAP[2]
TIMERx CAP[3]
TIMERx MAT[0]
TIMERx MAT[1]
TIMERx MAT[2]
TIMERx MAT[3]
•
•
•
•
•
32-bit timer/counter with programmable 32-bit prescaler
Up to four 32-bit capture channels per timer. These take a snapshot of the timer value
when an external signal connected to the TIMERx CAPn input changes state. A
capture event may also optionally generate an interrupt.
Four 32-bit match registers per timer that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
Up to four external outputs per timer corresponding to match registers, with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
Pause input pin (MSCSS timers only)
Timer pins
All information provided in this document is subject to legal disclaimers.
Pin names
CAPx[0]
CAPx[1]
CAPx[2]
CAPx[3]
MATx[0]
MATx[1]
MATx[2]
MATx[3]
Rev. 03 — 7 April 2010
Section 6.16.5
Section
IN
IN
IN
IN
Direction
OUT
OUT
OUT
OUT
6.12.3.
ARM9 microcontroller with CAN, LIN, and USB
for information on generation of these clocks.
Table 16
Description
TIMER x capture input 0
TIMER x capture input 1
TIMER x capture input 2
TIMER x capture input 3
TIMER x match output 0
TIMER x match output 1
TIMER x match output 2
TIMER x match output 3
Section 6.15.6
shows the timer pins (x runs from
for a description of these
LPC2939
© NXP B.V. 2010. All rights reserved.
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