C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 150

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously starting at P0.0 after prioritized
functions and skipped pins are assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
150
SF Signa ls
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
SF Signa ls Special Function Signals are not assigned by the crossbar. W hen these signals are enabled,
Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped
Port pin potentially assignable to peripheral
the CrossBar must be manually configured to skip their corresponding port pins.
i0 i1
0
0
1
0
2
0
P0SKIP[0:7]
3
0
P0
4
0
5
0
cnvstr
6
0
7
0
x1 x 2 vre f
0
1
Rev. 1.1
1
1
P1SKIP[0:7] = 0x03
2
0
3
0
P1
4
0
5
0
6
0
7
0
(*4-W ire SPI Only)
0
0
1
0
2
0
P2SKIP[0:7]
3
0
P2
4
0
5
0
6
0
7
0