C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 178

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
20.1. smaRTClock Interface
The smaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the smaRTClock internal regis-
ters listed in Table 20.1. The smaRTClock internal registers can only be accessed indirectly through the
smaRTClock Interface.
20.1.1. smaRTClock Lock and Key Functions
The smaRTClock Interface is protected with a lock and key function. The smaRTClock Lock and Key Reg-
ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric-
tions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes
are written, or an invalid read or write is attempted, further writes and reads to RTC0ADR and RTC0DAT
will be disabled until the next system reset. Once the smaRTClock interface is unlocked, software may per-
form accesses of the smaRTClock registers until an invalid access, the interface is locked, or a system
reset.
Reading the RTC0KEY register at any time will provide the smaRTClock Interface status and will not inter-
fere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1 lists
the definition of each status code.
20.1.2. Using RTC0ADR and RTC0DAT to Access smaRTClock Internal Registers
The smaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the smaRTClock internal register that will be targeted by subsequent reads or
writes. Prior to each read or write, BUSY (RTC0ADR.7) should be checked to make sure the smaRTClock
Interface is not busy performing another read or write operation. A smaRTClock Write operation is initiated
by writing to the RTC0DAT register. Below is an example of writing to a smaRTClock internal register.
An smaRTClock Read operation is initiated by setting the smaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
RTC0DAT until the next read or write operation. Below is an example of reading a smaRTClock internal
register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. smaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
smaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the begin-
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Step 1. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 2. Write 0x06 to RTC0ADR. This selects the internal RTC0CN register at smaRTClock
Step 3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
Step 1. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 2. Write 0x06 to RTC0ADR. This selects the internal RTC0CN register at smaRTClock
Step 3. Write ‘1’ to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
Step 4. Poll BUSY (RTC0ADR.7) until it returns a ‘0’.
Step 5. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
Address 0x06.
Address 0x06.
Rev. 1.1