Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 113

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Table 65. ADC Clock Prescale Register (ADCCP)
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Bit
Position
[0]
DIV2
[1]
DIV4
[2]
DIV8
[7:3]
ADC Clock Prescale Register
Value
(H)
0
1
0
1
0
1
0h
7
The ADC clock prescale register, listed in
clock to the ADC. When this register is programmed with
the ADC clock. DIV8 has the highest priority, DIV2 has the lowest priority.
Description
DIV2
Clock is not divided
System clock is divided by 2 for ADC clock
DIV4
Clock is not divided
System clock is divided by 4 for ADC clock
DIV8
Clock is not divided
System clock is divided by 8 for ADC clock
Reserved - must be 0.
6
Reserved
5
0
4
F76H
R/W
Table
3
65, is used to provide a divided system
DIV8
0h
Z8 Encore!
2
0
, the system clock is used for
Product Specification
Analog-to-Digital Converter
DIV4
1
0
®
F083A Series
DIV2
0
0
101