Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 46

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

HALT Mode
Peripheral Level Power Control
Power Control Register Definitions
PS026308-1207
Power Control Register 0
Executing the eZ8 CPU HALT instruction places the device into HALT mode. In HALT
mode, the operating characteristics are:
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The eZ8 CPU is brought out of HALT mode by any one of the following operations:
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To minimize current in HALT mode, all GPIO pins that are configured as digital inputs
must be driven to VDD when pull-up register bit is enabled or to one of power rail (VDD
or GND) when pull-up register bit is disabled.
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! F083A Series devices. Disabling a given peripheral minimizes its power
consumption.
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
Primary oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
WDT’s internal RC oscillator continues to operate.
If enabled, the WDT continues to operate.
All other on-chip peripherals continue to operate.
Interrupt
WDT time-out (interrupt or reset)
POR
VBO reset
External RESET pin assertion
Z8 Encore!
Product Specification
®
Low-Power Modes
F083A Series
34