Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 89

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PS026308-1207
the timer output alternate function is enabled, the timer output pin changes state (from low
to high or from high to low) at timer reset.
The steps for configuring a timer for GATED mode and for initiating the count are as
follows:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value. Writing
3. Write to the timer reload high and low byte registers to set the reload value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the timer control register to enable the timer.
7. Assert the timer input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external timer
input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the timer control register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the timer input signal, captures
the current count value. The capture value is written to the timer PWM high and low byte
registers. When the Capture event occurs, an interrupt is generated, the count value in the
timer high and low byte registers is reset to
INPCAP bit in TxCTL1 register is set to indicate that the timer interrupt is caused by an
input Capture event.
If no Capture event occurs, the timer counts up to the 16-bit compare value stored in the
timer reload high and low byte registers. On reaching the compare value, the timer
generates an interrupt, the count value in the timer high and low byte registers is reset to
0001H
that the timer interrupt is not caused by an input Capture event.
–
–
–
these registers only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting always begins at the reset value of
interrupt registers. By default, the timer interrupt is generated for both input
deassertion and Reload events. You configure the timer interrupt to be generated only
at the input Deassertion event or the Reload event by setting TICONFIG bit of the
TxCTL1 register.
and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate
Disable the timer
Configure the timer for GATED mode
Set the prescale value
0001H
and the counting resumes. The
Z8 Encore!
0001H
Product Specification
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®
F083A Series
Timers
77