Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 93
![KIT DEVELOPMENT F083A](/photos/9/25/92520/z8f083a0128zcog_sml.jpg)
Z8F083A0128ZCOG
Manufacturer Part Number
Z8F083A0128ZCOG
Description
KIT DEVELOPMENT F083A
Manufacturer
Zilog
Series
Z8 Encore! XP®r
Type
MCUr
Specifications of Z8F083A0128ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F083A
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F083A0128ZCOG
Manufacturer:
Zilog
Quantity:
1
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Table 53. Timer 0–1 Control Register 0 (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
Table 51. Timer 0–1 PWM High Byte Register (TxPWMH)
Table 52. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Timer 0–1 Control Registers
TMODEHI
R/W
R/W
R/W
7
0
7
0
7
0
PWMH and PWML—Pulse width modulator high and low bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the timer control register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in capture or CAPTURE/COMPARE modes.
Time 0–1 Control Register 0
The timer control register 0 (TxCTL0) and timer control register 1 (TxCTL1) determine
the timer operating mode. It also includes a programmable PWM deadband delay, two bits
to configure timer interrupt definition, and a status bit to identify, if the most recent timer
interrupt is caused by an input Capture event.
R/W
R/W
R/W
6
0
6
0
6
0
TICONFIG
R/W
R/W
R/W
5
0
5
0
5
0
Reserved
R/W
R/W
R/W
4
0
4
0
4
0
F04H, F0CH
F05H, F0DH
F06H, F0EH
PWMH
PWML
R/W
R/W
R/W
3
0
3
0
3
0
PWMD
R/W
R/W
R/W
Z8 Encore!
2
0
2
0
2
0
Product Specification
R/W
R/W
R/W
1
0
1
0
®
1
0
F083A Series
INPCAP
R/W
R/W
R/W
0
0
0
0
Timers
0
0
81
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