AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 17
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
6.2.2
6.2.3
6438ES–ATARM–21-Jun-10
Matrix Slaves
Masters to Slaves Access
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 6-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the DDR multi-port in the DDR multi-port Register (bit DDRMP_DIS) in the
Chip Configuration User Interface.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
• When the DDR multi-port is enabled (DDRMP_DIS=0), the ARM instruction and data are
• When the DDR multi-port is disabled (DDRMP_DIS=1), DDR Port 1 is dedicated to the LCD
respectively connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2
and DDR Port 3.
controller. The remaining masters share DDR Port 2 and DDR Port 3.
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
External Bus Interface
Internal Peripherals
AT91SAM9G45
17