AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 50
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
10.14 Image Sensor Interface (ISI)
10.15 8-channel DMA (DMA)
50
AT91SAM9G45
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Supports promiscuous mode where all valid frames are copied to memory
• Supports physical layer management through MDIO interface
• Supports Wake On Lan. The receiver supports Wake on LAN by detecting the following
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
• Preview scaler to generate smaller size image
• Acting as two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
• Channel Buffering
events on incoming receive frames:
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match
– Source/Destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
– Gather support for extracting fields from a system memory area into a contiguous
– User enabled auto-reloading of source, destination and control registers from initially
– Auto-loading of source, destination and control registers from system memory at end
– Unaligned system address to data transfer width supported in hardware
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
transfer
programmed values at the end of a block transfer
of block transfer in block chaining mode
6438ES–ATARM–21-Jun-10