AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 26

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

7.2.4.1
7.2.4.2
7.3
7.3.1
26
External Memories
AT91SAM9G45
DDRSDRC0 Multi-port DDRSDR Controller
BMS = 1, boot on embedded ROM
BMS = 0, boot on external memory
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
The system boots on Boot Program.
For optimization purpose, nothing else is done. To speed up the boot sequence user pro-
grammed software should perform a complete configuration:
The AT91SAM9G45 features a Multi-port DDR2 Interface and an External Bus Interface allow-
ing to connect to a wide range of external memories and to any parallel peripheral.
Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini-
mizes Transaction Latency.
• Boot on on-chip RC
• Enable the 32768 Hz oscillator
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
• Boot on on-chip RC
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
• Enable the 32768 Hz oscillator if best accuracy needed
• Program the PMC (main oscillator enable or bypass mode)
• Program and Start the PLL
• Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to
• Switch the main clock to the new value
• Supports AHB Transfers:
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
the new clock
– SPI DataFlash/SerialFlash connected on NPCS0 of the SPI0
– SDCard
– NandFlash
– EEPROM connected on TWI0
– Serial communication on a DBGU
– USB Device HS Port
– Word, Half Word, Byte Access.
6438ES–ATARM–21-Jun-10