AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 49
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
10.11 LCD Controller (LCDC)
10.12 Touch Screen Analog-to-Digital Converter (TSADC)
10.13 Ethernet 10/100 MAC (EMAC)
6438ES–ATARM–21-Jun-10
• Embedded 4-KByte dual-port RAM for endpoints
• Embedded 6 channels DMA controller
• Suspend/Resume logic
• Up to 2 or 3 banks for isochronous and bulk endpoints
• Seven endpoints:
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported.
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048 x 2048
• 8-channel ADC
• Support 4-wire resistive Touch Screen
• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC
• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
• Sleep Mode and conversion sequencer
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
– Endpoint 0: 64 bytes, 1 bank mode
– Endpoint 1 & 2: 1024 bytes, 2 banks mode, High Bandwidth, DMA
– Endpoint 3 & 4: 1024 bytes, 3 banks mode, DMA
– Endpoint 5 & 6: 1024 bytes, 3 banks mode, High Bandwidth, DMA
– Hardware or software trigger
– External trigger pin
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
AT91SAM9G45
49