DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 37

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Freescale Semiconductor
Data Valid for outputs
Master
Slave (after enable edge)
Data invalid
Master
Slave
Rise time
Master
Slave
Fall time
Master
Slave
1. Parameters listed are guaranteed by design.
SCLK (CPOL = 0)
SCLK (CPOL = 1)
Operating Conditions:
(Output)
(Output)
(Output)
(Input)
(Input)
MISO
MOSI
SS
Characteristic
Figure 3-18 SPI Master Timing (CPHA = 0)
V
SS
t
DS
= V
SSA
= 0 V, V
Master MSB out
56F803 Technical Data, Rev. 16
t
Table 3-12 SPI Timing
DH
MSB in
t
F
DD
t
DI
= V
t
t
CH
CL
SS is held High on master
DDA
t
C
Symbol
t
t
= 3.0–3.6V, T
DV
t
t
DI
R
F
t
t
CL
CH
Bits 14–1
Bits 14–1
Min
0
0
A
1
= –40° to +85°C, C
t
t
R
F
t
DV
Max
20.4
11.5
10.0
4.5
9.7
9.0
Serial Peripheral Interface (SPI) Timing
Master LSB out
t
t
F
R
Unit
LSB in
L
ns
ns
ns
ns
ns
ns
ns
ns
t
DI
50pF, f
(ref)
t
R
Figures 3-18, ,
Figures 3-18, ,
Figures 3-18, ,
Figures 3-18, ,
OP
See Figure
3-20,
3-20,
3-20,
3-20,
= 80MHz
3-21
3-21
3-21
3-21
37

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