DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 45
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DSP56F803EVM
Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor
Datasheets
1.CWH-UTP-ONCE-HE.pdf
(2 pages)
2.DSP56F803EVM.pdf
(68 pages)
3.DSP56F803BU80E.pdf
(52 pages)
Specifications of DSP56F803EVM
Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Controller Area Network (CAN) Timing
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detec-
tion takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the
fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
2. Parameters listed are guaranteed by design.
MSCAN_RX
CAN receive
data pin
T
(Input)
WAKEUP
Figure 3-27 Bus Wakeup Detection
56F803 Technical Data, Rev. 16
Freescale Semiconductor
45