DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 44

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
3.13 Controller Area Network (CAN) Timing
44
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. (1pf)
Operating Conditions: V
Baud Rate
Bus Wakeup detection
ADC Quiescent Current (both ADCs)
V
1. For optimum ADC performance, keep the minimum V
output code of 0.
2. V
DA
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. t
REF
-0.3V.
AIC
Quiescent Current (both ADCs)
REF
= 1/
must be equal to or less than V
ADC analog input
f
Characteristic
ADIC
Characteristic
SS
1
= V
Figure 3-26 Equivalent Analog Input Circuit
SSA
1
= 0 V, V
Table 3-16 ADC Characteristics
DDA
DD
Table 3-17 CAN Timing
56F803 Technical Data, Rev. 16
and must be greater than 2.7V. For optimal ADC performance, set V
= V
Symbol
DDA
T
I
2
Symbol
I
VREF
BR
ADC
WAKEUP
= 3.0–3.6 V, T
CAN
ADCIN
value > 25mV. Inputs less than 25mV may convert to a digital
Min
A
= –40× to +85×C, C
Min
5
3
2
Typ
50
12
L
£ 50pF, MSCAN Clock = 30MHz
4
Max
Max
16.5
1
Freescale Semiconductor
REF
Unit
to V
Mbps
mA
mA
Unit
μs
D-

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