MC56F8323EVM Freescale Semiconductor, MC56F8323EVM Datasheet - Page 60

KIT EVALUATION FOR MC56F8323

MC56F8323EVM

Manufacturer Part Number
MC56F8323EVM
Description
KIT EVALUATION FOR MC56F8323
Manufacturer
Freescale Semiconductor
Type
DSPr

Specifications of MC56F8323EVM

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8322 and MC56F8323
Data Bus Width
16 bit
Interface Type
RS-232
For Use With/related Products
MC56F8322, MC56F8323
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
60
IPR0
IPR1
IPR2
IPR3
IPR4
IPR5
IPR6
IPR7
IPR8
IPR9
VBA
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
IRQP5
ICTL
Register Acronym
Base Address +
$1D
$10
$12
$13
$14
$15
$16
$11
$A
$B
$C
$D
$E
$0
$1
$2
$3
$4
$5
$6
$7
$9
$F
$8
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F1A0)
56F8323 Technical Data, Rev. 17
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt 0 Match Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High Register
Fast Interrupt 1 Match Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
Interrupt Control Register
Register Name
Freescale Semiconductor
Section Location
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
5.6.30
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
Preliminary

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