MC56F8323EVM Freescale Semiconductor, MC56F8323EVM Datasheet - Page 76

• Manufacturer Part Number: MC56F8323EVM
• Description: KIT EVALUATION FOR MC56F8323
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8323EVM

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8322 and MC56F8323
• Data Bus Width: 16 bit
• Interface Type: RS-232
• For Use With/related Products: MC56F8322, MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.6.11.2
The contents of this register determine the location of the Vector Address Table. The value in this register
is used as the upper 13 bits of the interrupt vector address. The lower eight bits of the ISR address are
determined based upon the highest-priority interrupt; see
5.6.12
5.6.12.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; for details, see
results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become
the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being
declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector
number of each IRQ, refer to
5.6.13
5.6.13.1
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
76
Base + $B
Base + $C
RESET
RESET
Write
Write
Read
Read
Fast Interrupt 0 Match Register (FIM0)
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Interrupt Vector Base Address (VECTOR BASE ADDRESS)—
Bits 12–0
Reserved—Bits 15–7
Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
15
15
0
0
0
Part
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
14
14
0
0
0
5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected
13
13
Table
0
0
0
12
12
0
0
0
4-3.
56F8323 Technical Data, Rev. 17
11
11
0
0
0
10
10
0
0
0
VECTOR ADDRESS LOW
9
0
0
9
0
FAST INTERRUPT 0
8
0
0
8
0
Part 5.3.1
7
7
0
0
0
6
6
0
0
for details.
5
0
5
0
FAST INTERRUPT 0
4
4
0
0
3
3
0
0
Freescale Semiconductor
2
0
2
0
1
0
1
0
Preliminary
0
0
0
0