AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 230

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3.1
24.3.2
230
AT91SAM9R64/RL64 Preliminary
Write Access
Read Access
The only configuration required for ECC is the NAND Flash or the SmartMedia page size
(528/1056/2112/4224). Page size is configured setting the PAGESIZE field in the ECC Mode
Register (ECC_MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND
Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in
the ECC Parity Register (ECC_PR) and ECC NParity Register (ECC_NPR) are then valid and
locked until a new start condition occurs (read/write command followed by address cycles).
Once the flash memory page is written, the computed ECC code is available in the ECC Parity
Error (ECC_PR) and ECC_NParity Error (ECC_NPR) registers. The ECC code value must be
written by the software application in the extra area used for redundancy.
After reading the whole data in the main area, the application must perform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by the ECC controller. Please note that it is mandatory to read consecutively the entire
main area and the locations where Parity and NParity values have been previously stored to let
the ECC controller perform error detection.
The application can check the ECC Status Register (ECC_SR) for any detected errors.
It is up to the application to correct any detected error. ECC computation can detect four differ-
ent circumstances:
ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a
read/write command is detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used.
32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-
bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are
generated according to the schemes shown in
• No error: XOR between the ECC computation and the ECC code stored at the end of the
• Recoverable error: Only the RECERR flag in the ECC Status register (ECC_SR) is set. The
• ECC error: The ECCERR flag in the ECC Status Register is set. An error has been detected
• Non correctable error: The MULERR flag in the ECC Status Register is set. Several
NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Register
(ECC_SR).
corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity
Register (ECC_PR). The corrupted bit position in the concerned word is defined in the
BITADDR field in the ECC Parity Register (ECC_PR).
in the ECC code stored in the Flash memory. The position of the corrupted bit can be found
by the application performing an XOR between the Parity and the NParity contained in the
ECC code stored in the flash memory.
unrecoverable errors have been detected in the flash memory page.
Figure 24-2
and
Figure
24-3.
6289C–ATARM–28-May-09