AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 793

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.5.22
Name:
Access Type:
• FRCESTALL: Stall Handshake Request
0 = no effect.
1= If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
Note 1: In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT
Data = 1).
Note 2:These bits are updated for OUT transfer:
Note 3: For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/ERR_TRANS
bit to know if the toggle sequencing is correct or not.
Note 4: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
6289C–ATARM–28-May-09
00
01
10
11
SHRT_PCKT
NAK_OUT
IN endpoint: it indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the cur-
rent bank.
CONTROL and OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
– a new data has been written into the current bank.
– the user has just cleared the Received OUT Data bit to switch to the next bank.
31
23
15
7
TOGGLESQ_STA
Data0
Data1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
UDPHS Endpoint Status Register
ERR_FLUSH
NAK_IN/
30
22
14
Read-only
6
UDPHS_EPTSTAx [x=0..6]
BYTE_COUNT
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
FRCESTALL
29
21
13
5
ERR_FL_ISO
RX_SETUP/
28
20
12
4
–
AT91SAM9R64/RL64 Preliminary
BYTE_COUNT
TX_PK_RDY/
ERR_TRANS
27
19
11
BUSY_BANK_STA
3
–
TX_COMPLT
26
18
10
2
–
RX_BK_RDY/
KILL_BANK
25
17
CURRENT_BANK/
9
1
–
CONTROL_DIR
ERR_OVFLW
24
16
8
0
–
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