AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 713

MCU ARM9 64K SRAM 144-LFBGA

AT91SAM9R64-CU

Manufacturer Part Number
AT91SAM9R64-CU
Description
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9R64-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
49
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
144LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Figure 40-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x
40.6.2.3
40.6.2.4
6289C–ATARM–28-May-09
(Controller Output)
Write access to
AC97C_THRx
(AC97C_SR)
(AC97C_SR)
TXEMPTY
TXRDYCx
AC97FS
AC97TX
Slot #
AC‘97 Output Frame
Receive Operation
TAG
0
transfered to the shift register
The TXEMPTY flag in the AC’97 Controller Channel x Status Register (AC97C_CxSR) is set
when all requested transmissions for a channel have been shifted on the AC-link. The applica-
tion can either poll TXEMPTY flag in AC97C_CxSR or wait for an interrupt notice associated
with the same flag.
In most cases, the AC’97 Controller is embedded in chips that target audio player devices. In
such cases, the AC‘97 Controller is exposed to heavy audio transfers. Using the polling tech-
nique increases processor overhead and may fail to keep the required pace under an operating
system. In order to avoid these polling drawbacks, the application can perform audio streams by
using PDC connected to channel A, which reduces processor overhead and increases perfor-
mance especially under an operating system.
The PDC transmit counter values must be equal to the number of PCM samples to be transmit-
ted, each sample goes in one slot.
The AC’97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot
0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid
data or not. Slots 1 and 2 are used if the application performs control and status monitoring
actions on AC97 Codec control/status registers. Slots [3:12] are used according to the content of
the AC’97 Controller Output Channel Assignment Register (AC97C_OCA). If the application per-
forms many transmit requests on a channel, some of the slots associated to this channel or all of
them will carry valid data.
The AC’97 Controller can also receive data from AC‘97 Codec. Data is received in the channel’s
shift register and then transferred to the AC’97 Controller Channel x Read Holding Register. To
read the newly received data, the application must perform the following steps:
• Poll RXRDY flag in AC’97 Controller Channel x Status Register (AC97C_CxSR). x being one
• Read data from AC’97 Controller Channel x Read Holding Register.
ADDR
of the 2 channels.
CMD
1
transfered to the shift register
PCM L Front
DATA
CMD
2
PCM R Front
L Front
3
PCM
R Front
4
PCM
AT91SAM9R64/RL64 Preliminary
LINE 1
DAC
5
Center
6
PCM
L SURR
PCM
7
R SURR
PCM
8
PCM
LFE
9
LINE 2
DAC
10
11
HSET
DAC
CTRL
12
IO
713

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