AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 757

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.4.12.2
41.4.12.3
41.4.12.4
41.4.12.5
41.4.12.6
6289C–ATARM–28-May-09
Not Powered State
Entering Attached State
From Powered State to Default State (Reset)
From Default State to Address State (Address Assigned)
From Address State to Configured State (Device Configured)
Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a
host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Dis-
abling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to
GND pull-downs integrated in the hub downstream ports.
When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pull-
downs integrated in the hub downstream ports. When a device is attached to an hub down-
stream port, the device connects a 1.5 KΩ pull-up on FSDP. The USB bus line goes into IDLE
state, FSDP is pulled-up by the device 1.5 KΩ resistor to 3.3V and FSDM is pulled-down by the
15 KΩ resistor to GND of the host.
After pull-up connection, the device enters the powered state. The transceiver remains disabled
until bus activity is detected.
In case of low power consumption need, the device can be stopped. When the device detects
the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in
UDPHS_CTRL register.
The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register.
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked
flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered.
Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state,
the UDPHS software must:
In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled.
After a Set Address standard device request, the USB host peripheral enters the address state.
Warning: before the device enters address state, it must achieve the Status IN transaction of
the control transfer, i.e., the UDPHS device sets its new address once the TX_COMPLT flag in
the UDPHS_EPTCTL[0] register has been received and cleared.
To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN
flag in the UDPHS_CTRL register.
Once a valid Set Configuration standard request has been received and acknowledged, the
device enables endpoints corresponding to the current configuration. This is done by setting the
BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the UDPHS_EPTCFGx registers
and enabling them by setting the EPT_ENABL flag in the UDPHS_EPTCTLENBx registers, and,
optionally, enabling corresponding interrupts in the UDPHS_IEN register.
• Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0]
• Configure the Interrupt Mask Register which has been reset by the USB reset detection
• Enable the transceiver.
register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_INT_0 of the
UDPHS_IEN register. The enumeration then begins by a control transfer.
AT91SAM9R64/RL64 Preliminary
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