ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 41

• Manufacturer Part Number: ADUC841BSZ62-5
• Description: IC ADC/DAC 12BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC841BSZ62-5

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Core Processor: 8052
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 2.25KB
• Cpu Speed: 20MIPS
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ON-CHIP PLL
The ADuC842 and ADuC843 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (512) of
this to provide a stable 16.78 MHz clock for the system. The
ADuC841 operates directly from an external crystal. The core
can operate at this frequency or at binary submultiples of it to
allow power saving in cases where maximum core performance
is not required. The default core clock is the PLL clock divided
by 8 or 2.097152 MHz. The ADC clocks are also derived from
the PLL clock, with the modulator rate being the same as the
crystal oscillator frequency. The preceding choice of frequencies
ensures that the modulators and the core are synchronous,
regardless of the core clock rate. The PLL control register is
PLLCON.
Table 16. PLLCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
OSC_PD
LOCK
----
----
FINT
CD2
CD1
CD0
Description
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit.
This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal subsequently becomes disconnected, the PLL will rail.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 16.78 MHz
±20%.
Reserved. Should be written with 0.
Reserved. Should be written with 0.
Fast Interrupt Response Bit.
Set by the user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–0 bits (see below). Once user code has returned from an interrupt, the core resumes
code execution at the core clock selected by the CD2–0 bits.
Cleared by the user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core operates.
CD2
0
0
0
0
1
1
1
1
CD1
0
0
1
1
0
0
1
1
CD0
0
1
0
1
0
1
0
1
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Core Clock Frequency (MHz)
16.777216
8.388608
4.194304
2.097152 (Default Core Clock Frequency)
1.048576
0.524288
0.262144
0.131072
At 5 V the core clock can be set to a maximum of 16.78 MHz,
while at 3 V the maximum core clock setting is 8.38 MHz. The
CD bits should not be set to 0 on a 3 V part.
Note that on the ADuC841, changing the CD bits in PLLCON
causes the core speed to change. The core speed is crystal freq/
2
ADuC841 and should be written with 0.
PLLCON PLL
SFR Address
Power-On Default
Bit Addressable
CD
. The other bits in PLLCON are reserved in the case of the
ADuC841/ADuC842/ADuC843
Control Register
D7H
53H
No