ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 49

• Manufacturer Part Number: ADUC841BSZ62-5
• Description: IC ADC/DAC 12BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC841BSZ62-5

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Core Processor: 8052
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 2.25KB
• Cpu Speed: 20MIPS
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Bit No.
2
1
0
I2CADD
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD1
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD2
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD3
Function
SFR Address
Power-On Default
Bit Addressable
I2CDAT
Function
SFR Address
Power-On Default
Bit Addressable
The main features of the MicroConverter I
•
•
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
devices. Because each slave device has a unique 7-bit
2
C master can communicate with multiple slave
Name
I2CRS
I2CTX
I2CI
Description
I
Set by the user to reset the I
Cleared by the user code for normal I
I
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
2
2
2
C Reset Bit (Slave Mode Only).
C Direction Transfer Bit (Slave Mode Only).
C Interrupt Bit (Slave Mode Only).
I
Holds the first I
uC001 at www.analog.com/microconverter describes the format of the I
detail.
9BH
55H
No
I
Holds the second I
91H
7FH
No
I
Holds the third I
92H
7FH
No
I
Holds the fourth I
93H
7FH
No
I
Written by the user to transmit data over the I
received by the I
the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
9AH
00H
No
2
2
2
2
2
C Address Register
C Address Register
C Address Register
C Address Register
C Data Register
2
C interface are
2
2
C peripheral address for the part. It may be overwritten by user code. Application Note
2
2
C interface. Accessing I2CDAT automatically clears any pending I
C interface.
C peripheral address for the part. It may be overwritten by user code.
2
2
C peripheral address for the part. It may be overwritten by user code.
C peripheral address for the part. It may be overwritten by user code.
2
C operation.
Rev. 0 | Page 49 of 88
•
address, single master/slave relationships can exist at all
times even in a multislave environment.
Ability to respond to four separate addresses when
operating in slave mode.
2
C interface or read by user code to read data just
ADuC841/ADuC842/ADuC843
2
C standard 7-bit address in
2
C interrupt and