ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 80

• Manufacturer Part Number: ADUC841BSZ62-5
• Description: IC ADC/DAC 12BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC841BSZ62-5

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Core Processor: 8052
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 2.25KB
• Cpu Speed: 20MIPS
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ADuC841/ADuC842/ADuC843
Parameter
EXTERNAL DATA MEMORY WRITE CYCLE
t
t
t
t
t
t
t
t
t
WLWH
AVLL
LLAX
LLWL
AVWL
QVWX
QVWH
WHQX
WHLH
WR Pulse Width
Address Valid after ALE Low
Address Hold after ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup before WR
Data and Address Hold after WR
RD or WR High to ALE High
PORT 2 (O)
PSEN (O)
ALE (O)
WR (O)
t
AVLL
A16 A23
A0 A7
t
Figure 89. External Data Memory Write Cycle
LLAX
t
AVWL
t
LLWL
Rev. 0 | Page 80 of 88
Min
65
60
65
190
60
120
380
60
t
16 MHz Core Clk
QVWX
DATA
t
t
V8 A15
WLWH
QVWH
Max
130
Min
130
120
135
375
120
250
755
125
t
t
WHLH
WHQX
8 MHz Core Clock
Max
260
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns