MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 134

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Signal Descriptions
2-36
HRESET
SRESET
Signal List
RSTCONF /
PORESET/
TEXP
WE[0:3]
BE[0:3]
CS[0:3]
TEA
AT[0:3]
TRST
BI
TA
STS
OE
7, 12
7, 12
7, 12
7, 11
7
7
11
11, 12
11, 12
/
7
7
7
7
/
/
1
Voltage
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
13
13
Controlled
Slew Rate
Option?
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
Development and Debug
Drive
Load
(pF)
N/A
NA
NA
2
System Control
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set.
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
Reset State
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
s
TA
TEA
OE
RSTCONF until reset
negates.
Controlled by DBGC in the
reset configuration word.
See
CS[0:3]
Controlled by bit ATWC (bit
12) of the reset configuration
word. See
PORESET/TRST
HRESET
SRESET
Function After HRESET,
Table
PORESET/TRST
6-8.
Table
Freescale Semiconductor
6-8.