MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 20

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

15.7.2
15.7.3
15.7.4
15.7.5
15.7.6
15.7.7
15.7.7.1
15.7.7.2
15.7.7.3
15.7.7.4
15.7.7.5
15.7.7.6
15.7.7.7
15.7.7.8
15.7.7.9
15.7.7.10
15.7.7.11
15.8
15.8.1
15.8.2
15.8.2.1
15.8.2.2
15.8.3
15.8.4
15.8.5
15.8.6
15.8.7
15.8.8
15.8.9
15.8.10
15.8.11
15.8.12
16.1
16.2
16.2.1
16.3
16.3.1
Freescale Semiconductor
Paragraph
Number
SCI Queue Operation .................................................................................................. 15-59
Features ......................................................................................................................... 16-1
External Signals ............................................................................................................ 16-2
TouCAN Architecture ................................................................................................... 16-3
SCI Control Register 0 (SCCxR0) .......................................................................... 15-46
SCI Control Register 1 (SCCxR1) .......................................................................... 15-47
SCI Status Register (SCxSR) .................................................................................. 15-48
SCI Data Register (SCxDR) ................................................................................... 15-50
SCI Pins .................................................................................................................. 15-51
SCI Operation ......................................................................................................... 15-51
Queue Operation of SCI1 for Transmit and Receive .............................................. 15-59
Queued SCI1 Status and Control Registers ............................................................ 15-59
QSCI1 Transmitter Block Diagram ........................................................................ 15-62
QSCI1 Additional Transmit Operation Features .................................................... 15-63
QSCI1 Transmit Flow Chart Implementing the Queue .......................................... 15-65
Example QSCI1 Transmit for 17 Data Bytes ......................................................... 15-67
Example SCI Transmit for 25 Data Bytes .............................................................. 15-68
QSCI1 Receiver Block Diagram ............................................................................. 15-70
QSCI1 Additional Receive Operation Features ...................................................... 15-70
QSCI1 Receive Flow Chart Implementing the Queue ............................................ 15-73
QSCI1 Receive Queue Software Flow Chart ......................................................... 15-74
Example QSCI1 Receive Operation of 17 Data Frames ......................................... 15-75
TouCAN Signal Sharing ........................................................................................... 16-3
Tx/Rx Message Buffer Structure .............................................................................. 16-4
Definition of Terms ............................................................................................ 15-51
Serial Formats ..................................................................................................... 15-52
Baud Clock ......................................................................................................... 15-52
Parity Checking .................................................................................................. 15-53
Transmitter Operation ......................................................................................... 15-54
Receiver Operation ............................................................................................. 15-55
Receiver Bit Processor ........................................................................................ 15-55
Receiver Functional Operation ........................................................................... 15-57
Idle-Line Detection ............................................................................................. 15-58
Receiver Wake-Up .............................................................................................. 15-58
Internal Loop Mode ............................................................................................ 15-59
QSCI1 Control Register (QSCI1CR) .................................................................. 15-60
QSCI1 Status Register (QSCI1SR) .................................................................... 15-61
MPC561/MPC563 Reference Manual, Rev. 1.2
CAN 2.0B Controller Module
Contents
Chapter 16
Title
Number
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