MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 372

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

External Bus Interface
Table 9-3
access.
Note: “—” denotes a byte not driven during that write cycle.
9.5.7
The external bus design provides for a single bus master at any one time, either the MPC561/MPC563 or
an external device. One or more of the external devices on the bus can have the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by
the internal on-chip arbiter. In the latter case, the system is optimized for one external bus master besides
the MPC561/MPC563. The arbitration configuration (external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that
needs the bus asserts BR. The device then waits for the arbiter to assert BG. In addition, the new master
must look at BB to ensure that no other master is driving the bus before it can assert BB to assume
ownership of the bus. Any time the arbiter has taken the bus grant away from the master and the master
wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed. The
MPC561/MPC563, however, guarantees data coherency for access to a small port size and for decomposed
bursts. This means that the MPC561/MPC563 will not release the bus before the completion of the
transactions that are considered atomic.
9-32
lists the patterns of the data transfer for write cycles when the MPC561/MPC563 initiates an
Arbitration Phase
Half-word
Transfer
Word
Size
Byte
TSIZE[0:1]
01
01
01
01
10
10
00
Table 9-3. Data Bus Contents for Write Cycles
MPC561/MPC563 Reference Manual, Rev. 1.2
Address
[30:31]
ADDR
00
01
10
11
00
10
00
Figure 9-24
DATA
[0:7]
OP0
OP1
OP2
OP3
OP0
OP2
OP0
describes the basic protocol for bus arbitration.
External Data Bus Pattern
[8:15]
DATA
OP1
OP3
OP1
OP3
OP1
—
—
[16:23]
DATA
OP2
OP2
OP2
—
—
—
—
Freescale Semiconductor
[24:31]
DATA
OP3
OP3
OP3
—
—
—
—