MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 217

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Base Address Register
Figure
Each table entry must contain a branch absolute (ba) instruction to the first instruction of an interrupt
service routine. Each table entry occupies two words (eight bytes) to support decompression on mode,
where a branch instruction can be more than 32 bits long.
The memory space allocated for the external interrupt relocation table is up to 2 Kbytes. If part of the
external interrupt relocation table entry is not used, it may be utilized for another purpose such as
instruction code space or data space.
In order to activate the external interrupt relocation feature, the following steps are required:
Freescale Semiconductor
1. Program the EIBADR register to the external interrupt branch table base address. See
2. Set the MSR[IP] bit.
3. Set the BBCMCR[EIR] bit. See
4-3.
Section 4.6.2.5, “External Interrupt Relocation Table Base Address Register
(BBCMCR),” for programming details.
If both the enhanced external interrupt relocation and exception table
relocation functions are activated simultaneously, the final external interrupt
vector is defined by EEIR mechanism.
When the EEIR function is activated, any branch instruction execution with
the 0xFFF0 0500 target address may cause unpredictable program
execution.
(EIBADR).” This is the base address of a branch table. See
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 4.6.2.1, “BBC Module Configuration Register
NOTE
Burst Buffer Controller 2 Module
Table 6-4
(EIBADR).”
and
4-11