MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 631

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

15.5.3
DDRQS assigns QSPI pin as an input or an output regardless of whether the QSPI submodule is enabled
or disabled. All QSPI pins are configured during reset as general-purpose inputs.
This register does not affect SCI operation. The TXD1 and TXD2 remain output pinsdedicated to the SCI
submodules, and the RXD1and RXD2 pins remain input pins dedicated to the SCI submodules.
Freescale Semiconductor
Note: See bit descriptions in
SRESET
Bits
8:15
Field
Addr
0
1
2
3
4
5
6
7
PORTQS Data Direction Register (DDRQS)
MSB
—
0
QPAPCS3
QPAPCS2
QPAPCS1
QPAPCS0
QPAMOSI
QPAMISO
DDRQS
Name
QPAPC
—
—
S3
1
Figure 15-8. PORTQS Pin Assignment Register (PQSPAR)
QPAPC
Table 15-11
S2
Reserved
0 Pin is assigned QGPIO3
1 Pin is assigned PCS3 function
0 Pin is assigned QGPIO2
1 Pin is assigned PCS2 function
0 Pin is assigned QGPIO3
1 Pin is assigned PCS1 function
0 Pin is assigned QGPIO0
1 Pin is assigned PCS0 function
Reserved
0 Pin is assigned QGPIO5
1 Pin is assigned MOSI function
0 Pin is assigned QGPIO4
1 Pin is assigned MISO function
PORSTQS data direction register. See <XrefBlue>Section 15.5.3, “PORTQS Data
Direction Register (DDRQS),” on page 15-13.
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-10. PQSPAR Bit Descriptions
QPAPC
S1
3
QPAPC
S0
4
0000_0000_0000_0000
—
5
0x30 5016
QPAMOSI QPAMISO
6
Description
7
8
Queued Serial Multi-Channel Module
9
10
DDRQS*
11
12
13
14
LSB
15
15-13