ST10F276-6QR3 STMicroelectronics, ST10F276-6QR3 Datasheet - Page 168

• Manufacturer Part Number: ST10F276-6QR3
• Description: MCU 16BIT 832K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-6QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Register set
168/231
BUSCON4 (FF1Ah / 8Dh)
Table 78.
CSWEN4 CSREN4 RDYPOL4 RDYEN4
RW
15
BUSACTx
RDYPOLx
ALECTLx
CSWENx
CSRENx
RDYENx
RWDCx
MTTCx
MCTC
BTYP
Bit
RW
14
BUSCON4 description
13
Memory cycle time control (number of memory cycle time wait-states)
0000: 15 wait-states (Number of wait-states = 15 - [MCTC]).
. . .
1111: No wait-states.
Read/Write delay control for BUSCONx
0: With read/write delay, the CPU inserts 1 TCL after falling edge of ALE.
1: No read/write delay, RW is activated after falling edge of ALE.
Memory tristate time control
0: 1 wait-state.
1: No wait-state.
External bus configuration
00: 8-bit Demultiplexed Bus
01: 8-bit Multiplexed Bus
10: 16-bit Demultiplexed Bus
11: 16-bit Multiplexed Bus
Note: For BUSCON0 BTYP is defined via PORT0 during reset.
ALE lengthening control
0: Normal ALE signal.
1: Lengthened ALE signal.
Bus active control
0: External bus disabled.
1: External bus enabled (within the respective address window, see ADDRSEL).
Ready input enable
0: External bus cycle is controlled by bit field MCTC only.
1: External bus cycle is controlled by the READY input signal.
Ready active level control
0: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY
pin.
1: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY
pin.
Read chip select enable
0: The CS signal is independent of the read command (RD).
1: The CS signal is generated for the duration of the read command.
Write chip select enable
0: The CS signal is independent of the write command (WR, WRL, WRH).
1: The CS signal is generated for the duration of the write command.
RW
12
11
-
BUSACT4 ALECTL4
RW
10
RW
9
SFR
Function
8
-
7
BTYP
RW
6
MTTC4 RWDC4
RW
5
RW
Reset value: 0000h
4
ST10F276E
3 2 1 0
MCTC
RW