ST10F276-6QR3 STMicroelectronics, ST10F276-6QR3 Datasheet - Page 189

• Manufacturer Part Number: ST10F276-6QR3
• Description: MCU 16BIT 832K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-6QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F276E
Input leakage and external circuit
The series resistor utilized to limit the current to a pin (see R
with a large source impedance, can lead to a degradation of A/D converter accuracy when
input leakage is present.
Data about maximum input leakage current at each pin is provided in
characteristics. Input leakage is greatest at high operating temperatures and in general
decreases by one half for each 10° C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming V
an input leakage of 100nA acting though an R
error of exactly one count (5mV); if the resistance were 100kΩ, the error would become two
counts.
Eventual additional leakage due to external clamping diodes must also be taken into
account in computing the total leakage affecting the A/D converter measurements. Another
contribution to the total leakage is represented by the charge sharing effects with the sam-
pling capacitance: C
the conversion rate of a single channel (maximum when fixed channel continuous conver-
sion mode is selected), it can be seen as a resistive path to ground. For instance, assuming
a conversion rate of 250 kHz, with C
1 / f
the error induced by the voltage partitioning between this resistance (sampled voltage on
C
respect the following relation:
The formula above places constraints on external network design, in particular on resistive
path.
A second aspect involving the capacitance network must be considered. Assuming the three
capacitances C
equivalent circuit shown in
close), a charge sharing phenomena is installed.
Figure 48. Charge sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see
S
) and the sum of R
C
C
S
, where f
V
V
V
V
CS
A
A2
A1
F
, C
C
1
represents the conversion rate at the considered channel). To minimize
P1
S
S
and C
Voltage Transient on C
being substantially a switched capacitance, with a frequency equal to
+ R
F
Figure
P2
+ R
2
are initially charged at the source voltage V
V
L
A
+ R
⋅
47), when the sampling phase is started (A/D switch
R S
------------------------------------------------------------------------------
S
+
SW
equal to 4pF, a resistance of 1MΩ is obtained (R
R F
S
+ R
+
R L
R
EQ
AD
+
T
L
R SW
S
, the external circuit must be designed to
= 50kΩ of external resistance leads to an
∆V < 0.5 LSB
+
t
R AD
<
1
-- - LSB
2
τ
τ
1
2
L
< (R
= R
in
L
SW
Figure
(C
Electrical characteristics
S
+ R
+ C
Figure
Chapter 23: Electrical
AD
P1
47), in combination
) C
+ C
S
A
<< T
P2
(refer to the
48):
)
S
AREF
189/231
= 5V),
EQ
=