ST10F276-6QR3 STMicroelectronics, ST10F276-6QR3 Datasheet - Page 55

• Manufacturer Part Number: ST10F276-6QR3
• Description: MCU 16BIT 832K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-6QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F276E
5.3.3
5.3.4
ST10 Configuration in UART BSL (RS232 or K-Line)
When the ST10F276E enters BSL mode on UART, the configuration shown in
automatically set (values that deviate from the normal reset values are marked in bold).
Table 30.
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin TxD0 is configured as output, so the ST10F276E can
return the acknowledge byte. Even if the internal IFLASH is enabled, a code cannot be
executed from it.
Loading the start-up code
After sending the acknowledge byte, the BSL enters a loop to receive 32 bytes via ASC0.
These bytes are stored sequentially into locations 00’FA40
allowing up to 16 instructions to be placed into the RAM area. To execute the loaded code
the BSL then jumps to location 00’FA40H, that is, the first loaded instruction. The bootstrap
loading sequence is now terminated; however, the ST10F276E remains in BSL mode. The
initially loaded routine will most probably load additional code or data, as an average
application is likely to require substantially more than 16 instructions. This second receive
loop may directly use the pre-initialized interface ASC0 to receive data and store it in
arbitrary user-defined locations.
This second level of loaded code may be
●
●
●
Watchdog timer
Register SYSCON
Context Pointer CP
Register STKUN
Stack Pointer SP
Register STKOV
Register BUSCON0
Register S0CON
Register S0BG
P3.10 / TXD0
DP3.10
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
the final application code
another, more sophisticated, loader routine that adds a transmission protocol to
enhance the integrity of the loaded code or data
a code sequence to change the system configuration and enable the bus interface to
store the received data into external memory
Function or register
ST10 configuration in UART BSL mode (RS232 or K-line)
Disabled
0400
FA00
FA00
FA40
FC00
acc. to startup config.
8011
acc. to ‘00’ byte
‘1’
‘1’
H
H
H
H
H
H
(1)
Access
(2)
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
H
through 00’FA5F
Notes
Bootstrap loader
H
Table 30
of the IRAM,
55/231
is