S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 1029

no-image

S912XEP100J5MAG

Manufacturer Part Number
S912XEP100J5MAG
Description
MCU 64K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S912XEP100J5MAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEP100J5MAG
Manufacturer:
FREESCALE
Quantity:
962
Part Number:
S912XEP100J5MAG
Manufacturer:
FREESCALE
Quantity:
2 400
Part Number:
S912XEP100J5MAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S912XEP100J5MAG
Manufacturer:
FREESCALE
Quantity:
2 400
Part Number:
S912XEP100J5MAG
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S912XEP100J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
27.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Freescale Semiconductor
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
Field
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
7
Section 27.4.1, “Flash Command Operations,”
Figure 27-4. FTM512K3 Register Summary (continued)
0
6
Figure 27-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
Table 27-9
MC9S12XE-Family Reference Manual , Rev. 1.23
6
Table 27-8. FCLKDIV Field Descriptions
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
5
CAUTION
0
4
Description
4
FDIV[6:0]
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
0
3
for more information.
3
0
2
2
0
1
1
0
0
0
1029

Related parts for S912XEP100J5MAG