S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 772

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 Serial Peripheral Interface (S12SPIV5)
21.3.2.4
Read: Anytime
Write: Has no effect
772
Module Base +0x0003
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SPPR2
Reset
SPTEF
MODF
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
SPIF
1
1
1
1
1
1
1
1
1
1
7
5
4
W
R
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
0 Transfer not yet complete.
1 New data copied to SPIDR.
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 21.3.2.2, “SPI Control Register 2
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Table 21-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
SPI Status Register (SPISR)
0
7
SPPR1
1
1
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
SPPR0
0
0
1
1
1
1
1
1
1
1
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 21-6. SPI Status Register (SPISR)
Table 21-8. SPISR Field Descriptions
SPTEF
5
1
SPR2
1
1
0
0
0
0
1
1
1
1
(SPICR2)”. The flag is cleared automatically by a read of the SPI status
MODF
SPR1
0
4
1
1
0
0
1
1
0
0
1
1
Description
Table
SPR0
0
1
0
1
0
1
0
1
0
1
0
0
21-9.
3
Baud Rate
Divisor
1792
1024
2048
2
0
0
896
128
256
512
16
32
64
Freescale Semiconductor
0
0
1
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
27.90 kbit/s
13.95 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
Baud Rate
Table
21-10.
0
0
0