S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 337

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X, the 16-bit address bus for
the XGATE module and an information byte, which contains a source/destination bit to indicate whether
the stored address was a source address or destination address.
MARK1
MARK2
SUB_1
ADDR1
IRQ_ISR LDAB
MARK1
IRQ_ISR LDAB
SUB_1
ADDR1
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Destination address of RTI, RTS, and RTC instructions.
Vector address of interrupts, except for SWI and BDM vectors
Source address of taken conditional branches
Destination address of indexed JAL instructions.
First XGATE code address in a thread
LDX
JMP
NOP
BRN
NOP
DBNE
STAB
RTI
LDX
JMP
STAB
RTI
BRN
NOP
DBNE
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
The execution flow taking into account the IRQ is as follows
#SUB_1
0,X
*
A,PART5
#$F0
VAR_C1
#SUB_1
0,X
#$F0
VAR_C1
*
A,PART5
MC9S12XE-Family Reference Manual Rev. 1.23
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
;
;
;
;
;
NOTE
Chapter 8 S12X Debug (S12XDBGV3) Module
337