S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 387

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8.1.13 Index Register plus Register Offset (IDR)
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
10.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
10.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
10.8.2
10.8.2.1
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
The same set of modes is available for the store instructions
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LDB
STW
LDB
STW
LDB
STW
LDL
LDW
LDB
STB
STW
Instruction Summary and Usage
Load & Store Instructions
R4,(R1,R2)
R4,(R1,R2)
R4,(R1,R2+)
R4,(R1,R2+)
R4,(R1,-R2)
R4,(R1,-R2)
RD,#IMM8
RD,(RB,RI)
RD,(RB, RI+)
RS,(RB, RI)
RS,(RB, RI+)
MC9S12XE-Family Reference Manual Rev. 1.23
; loads a byte from (R1+R2) into R4
; stores R4 as a word to (R1+R2)
; loads a byte from (R1+R2) into R4, R2+=1
; stores R4 as a word to (R1+R2), R2+=2
; R2 -=1, loads a byte from (R1+R2) into R4
; R2 -=2, stores R4 as a word to (R1+R2)
; loads an immediate 8 bit value to the lower byte of RD
; loads data using RB+RI as effective address
; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
; stores data using RB+RI as effective address
; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.
Chapter 10 XGATE (S12XGATEV3)
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