S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 1303

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x0240–0x027F Port Integration Module (PIM) Map 5 of 6 (continued)
0x0280–0x02BF MSCAN (CAN4) Map
Freescale Semiconductor
Address
Address
0x027C
0x027D
0x028C
0x0278
0x0279
0x027A
0x027B
0x027E
0x027F
0x0280
0x0281
0x0282
0x0283
0x0284
0x0285
0x0286
0x0287
0x0288
0x0289
0x028A
0x028B
CAN4TBSEL
CAN4RFLG
CAN4TARQ
CAN4BTR0
CAN4BTR1
CAN4TFLG
CAN4CTL0
CAN4CTL1
CAN4RIER
CAN4TAAK
CAN4TIER
CAN4IDAC
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
Reserved
PT0AD1
PT1AD1
Name
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R PT0AD1
R PT1AD1
R DDR0AD1
R DDR1AD1
R RDR0AD1
R RDR1AD1
R PER0AD1
R PER1AD1
R
R
R
R
R
R
R
R
R
R
R
R
R
RXFRM
WUPIF
WUPIE
SAMP
CANE
SJW1
Bit 7
Bit 7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
MC9S12XE-Family Reference Manual Rev. 1.23
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
CLKSRC
PT0AD1
PT1AD1
TSEG22
RXACT
CSCIF
CSCIE
SJW0
Bit 6
Bit 6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
RSTATE1
PT0AD1
PT1AD1
TSEG21
RSTAT1
LOOPB
CSWAI
IDAM1
BRP5
Bit 5
Bit 5
5
5
5
5
5
5
5
5
0
0
0
0
0
0
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
RSTATE0
TSEG20
PT0AD1
PT1AD1
RSTAT0
SYNCH
LISTEN
IDAM0
BRP4
Bit 4
Bit 4
4
4
4
4
4
4
4
4
0
0
0
0
0
0
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
TSTATE1
TSEG13
PT0AD1
PT1AD1
TSTAT1
BORM
BRP3
TIME
Bit 3
Bit 3
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
Appendix E Detailed Register Address Map
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1A1D
TSTATE0
ABTRQ2
TSEG12
PT0AD1
PT1AD1
ABTAK2
TSTAT0
TXEIE2
WUPM
IDHIT2
WUPE
BRP2
TXE2
Bit 2
Bit 2
TX2
2
2
2
2
2
2
2
2
0
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
ABTRQ1
PT0AD1
PT1AD1
TSEG11
ABTAK1
SLPRQ
TXEIE1
IDHIT1
SLPAK
OVRIF
OVRIE
BRP1
TXE1
Bit 1
Bit 1
TX1
1
1
1
1
1
1
1
1
0
DDR0AD1
DDR1AD1
RDR0AD1
RDR1AD1
PER0AD1
PER1AD1
ABTRQ0
PT0AD1
PT1AD1
TSEG10
ABTAK0
INITRQ
TXEIE0
INITAK
IDHIT0
RXFIE
BRP0
TXE0
Bit 0
Bit 0
RXF
TX0
0
0
0
0
0
0
0
0
0
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