S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 522

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
13.3.2.9
This read-only register contains the Conversion Complete Flags CCF[15:0].
Read: Anytime
Write: Anytime, no effect
522
Module Base + 0x000A
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
CCF[15:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
15–0
W
R
15
0
Conversion Complete Flag n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete
flag is set at the end of each conversion in a sequence. The flags are associated with the conversion position in
a sequence (and also the result register number). Therefore in non-fifo mode, CCF[8] is set when the ninth
conversion in a sequence is complete and the result is available in result register ATDDR8; CCF[9] is set when
the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth.
If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete flag
is only set if comparison with ATDDRn is true and if ACMPIE=1 a compare interrupt will be requested. In this
case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the
end of the conversion but is lost.
In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) or D) will be overwritten by the set.
0 Conversion number n not completed or successfully compared
1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn.
ATD Status Register 2 (ATDSTAT2)
= Unimplemented or Reserved
If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare
operator CMPGT[n] is true. (No result available in ATDDRn)
A flag CCF[n] is cleared when one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0, write “1” to CCF[n]
C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn
D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn
14
0
13
0
12
Figure 13-11. ATD Status Register 2 (ATDSTAT2)
0
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 13-19. ATDSTAT2 Field Descriptions
11
0
10
0
0
9
CCF[15:0]
0
8
Description
0
7
0
6
0
5
0
4
0
3
Freescale Semiconductor
2
0
0
1
0
0