S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 490
S912XEP100J5MAG
Manufacturer Part Number
S912XEP100J5MAG
Description
MCU 64K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S912XEP100J5MAG.pdf
(1328 pages)
Specifications of S912XEP100J5MAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4.1.2
The clock generator creates the clocks used in the MCU (see
on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see
switched to PLLCLK running at its minimum frequency f
visible at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus
Clock. But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
490
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
EXTAL
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
XTAL
Condition
OSCILLATOR
Gating
System Clocks Generator
LOOP (IIPLL)
= Clock Gate
PHASE
LOCK
OSCCLK
PLLCLK
Monitor
Clock
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 11-16. System Clocks Generator
Section 11.4.2.2, “Self Clock
PLLSEL or SCM
1
0
1
0
SCM
STOP(PSTP, PCE),
STOP(PSTP, PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
SYSCLK
STOP
SCM
. The Bus Clock is used to generate the clock
STOP
Figure
Mode”) Oscillator clock source is
11-16). The gating condition placed
÷2
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
Core Clock
Bus Clock
Oscillator
Clock
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