MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 49

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
SD1
SD2
SD3
SD6
ID
ADDR
RAS
CAS
SDCLK
SDCLK
WE
CS
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Address setup time
SD6
Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins
(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is
defined as 80% of signal value and “low” is defined as 20% of signal value.
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value, and “low” is defined as 50% of
signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM
CLK parameters are measured at the crossing point of SDCLK and SDCLK
(inverted clock).
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 34
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
BA
i.MX35 Applications Processors for Automotive Products, Rev. 9
indicates SDRAM requirements. All output signals are driven by
SD7
Table 35. SDRAM Refresh Timing Parameters
Figure 29. SDRAM Refresh Timing Diagram
SD11
Parameter
NOTE
SD10
SD1
SD3
Symbol
tCH
tCK
tCL
tAS
SD2
SD10
Min.
3.4
3.4
7.5
1.8
ROW/BA
Max.
4.1
4.1
—
—
Unit
ns
ns
ns
ns
49