MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 70

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.13.1
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4
Figure 48
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
4.9.13.1.5
Figure 49
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
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DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_HSYNC
DISPB_D3_DATA
DISPB_D3_DRDY
DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
DISPB_D3_HSYNC causes the panel to start a new line.
DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_CLK
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
Synchronous Interfaces
Interface to Active Matrix TFT LCD Panels, Functional Description
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels
i.MX35 Applications Processors for Automotive Products, Rev. 9
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n – 1
m – 1
Freescale Semiconductor
LINE n
m