MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 91

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 66
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Freescale Semiconductor
DISPB_SER_RS
DISPB_SER_RS
DISPB_SD_D_CLK
DISPB_D#_CS
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
DISPB_SD_D
(Input)
DISPB_SD_D
(Output)
DISPB_SD_D
(Input)
depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
Figure 66. 5-Wire Serial Interface (Type 2) Timing Diagram
i.MX35 Applications Processors for Automotive Products, Rev. 9
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
1 display IF
clock cycle
clock cycle
Preamble
Preamble
Write
Read
RW
RW
D7
D7
D6
D6
D5
D5
D4
Input data
D4
Output data
D3
D3
D2
D2
1 display IF
clock cycle
1 display IF
clock cycle
D1
D1
D0
D0
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