MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 87

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
These conditions may be device-specific.
2
3
4
5
6
7
8
Freescale Semiconductor
IP35 Controls setup time for write
IP36 Controls hold time for write
IP37 Slave device data delay
IP38 Slave device data hold time
IP39 Write data setup time
IP40 Write data hold time
IP41 Read period
IP42 Write period
IP43 Read down time
IP44 Read up time
IP45 Write down time
IP46 Write up time
IP47 Read time point
Tdicdr
Tdi cuw
Tdicpw
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
Tdicpr
Tdicur
Tdicdw
ID
Display interface clock period value for read:
Display interface clock period value for write:
Display interface clock down time for read:
Display interface clock up time for read:
Display interface clock down time for write:
Display interface clock up time for write:
This parameter is a requirement to the display connected to the IPU
=
=
=
=
=
=
1
-- - T
2
1
-- - T
2
T HSP_CLK cei l
1
-- - T
2
T HSP_CLK ceil
1
-- - T HSP_CLK ceil
2
Table 55. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
HSP_CLK
HSP_CLK
HSP_CLK
Parameter
⋅
⋅
3
⋅
2
⋅
⋅
cei l
ce il
5
7
⋅
cei l
9
6
DISP#_IF_CLK_PER_RD
--------------------------------------------------------------- -
4
DISP#_IF_CLK_PER_WR
----------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_RD
-------------------------------------------------------------------------------
2 DISP#_IF_CLK_UP_RD
--------------------------------------------------------------------
2 DISP#_IF_CLK_UP_WR
--------------------------------------------------------------------- -
⋅
2 DISP#_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
HSP_CLK_PERIOD
⋅
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
i.MX35 Applications Processors for Automotive Products, Rev. 9
HSP_CLK_PERIOD
8
8
Symbol
Tdicpw Tdicpw – 1.5
Tdicdw Tdicdw – 1.5
Tdicuw Tdicuw – 1.5
Tdcsw
Tdchw Tdicpw – Tdicdw – 1.5
Tdicpr
Tdicdr
Tdicur
Tracc
Tdrp
Troh
Tdh
Tds
Tdicuw – 1.5
0
Tdrp – Tlbd – Tdicdr
+ 1.5
Tdicdw – 1.5
Tdicpw – Tdicdw – 1.5
Tdicpr – 1.5
Tdicdr – 1.5
Tdicur – 1.5
Tdrp – 1.5
Min.
Tdicuw
Tdicpw – Tdicdw
Tdicdw
Tdicpw – Tdicdw
Tdicpr
Tdicpw
Tdicdr
Tdicur
Tdicdw
Tdicuw
Tdrp
Typ.
—
—
1
Tdrp
Tdicpr – Tdicdr – 1.5
Tdicpr + 1.5
Tdicpw + 1.5
Tdicdr + 1.5
Tdicur + 1.5
Tdicdw + 1.5
Tdicuw + 1.5
Tdrp + 1.5
1.5
9
– Tlbd
Max.
—
—
—
—
10
– Tdicur –
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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